The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to semiconductor memory devices.
Memory devices are known in the art for storing electronic data in a wide variety of electronic devices and applications. A typical memory device comprises a plurality of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line, and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (xe2x80x9c0xe2x80x9d) bit or a one (xe2x80x9c1xe2x80x9d) bit. For example, a memory cell may be defined as either being a xe2x80x9cprogrammedxe2x80x9d cell or an xe2x80x9cerasedxe2x80x9d cell, where, according to one particular convention, a programmed cell is representative of a xe2x80x9c0xe2x80x9d bit, and an erased cell is representative of a xe2x80x9c1xe2x80x9d bit.
Memory cells are grouped into memory sectors, where each memory sector includes a number of memory cells. For example, a memory sector can include an array of memory cells arranged into 1024 bit lines and 512 word lines. During an erase operation, all the memory cells within a target memory sector are erased. For a, negative gate erase memory device, this erase operation involves applying a large negative voltage to the gate of each memory cell within the target memory sector, and applying a large positive voltage to the well of each memory cell within the target memory sector. Conventionally, the large negative voltage supplied to the gate is provided by a single sector supply voltage by way of a pass gate. Thus, when the pass gate is enabled during the erase operation, the single sector supply voltage is supplied to each word line of the target memory sector.
Defects to the word lines within a memory sector can occur during memory fabrication. Such defects include adjacent word lines being shorted together and individual word lines being broken, for example. These defects create serious problems during a memory erase operation. As described above, a single sector supply voltage is provided to each word line of a target memory sector during an erase operation. When this voltage is supplied to a defective word line during a memory erase operation, the memory cell associated with the defective word line become overerased cells, and as a result, these overerased cells will leak excessively, ultimately causing the memory device to fail. Currently, there are no satisfactory solutions to deal with this problem. Instead, manufacturers typically acknowledge the existence of a certain level of defect density in a memory device, and disable memory sectors having defective word lines from operation. Unfortunately, this approach results in significantly reduced yield. In order to provide sufficient capacity, redundant memory sectors are required, resulting in increased silicon area and increased device size, both of which are undesirable. Accordingly, there exists a strong need in the art for a memory circuit for providing word line redundancy in a memory sector during memory erase operations, which results in reduced silicon area, reduced device size and increased yield in a memory device.
The present invention is directed to a memory circuit for providing word line redundancy in a memory sector during memory erase operations. The present invention addresses and resolves the need in the art for a memory circuit which results in reduced silicon area, reduced device size and increased yield in a memory device. According to one exemplary embodiment, the memory circuit comprises a memory sector having a plurality of memory cells. Each of the plurality of memory cells has a gate connected to a corresponding word line, where each corresponding word line is further connected to an output of a corresponding decoding circuit. Each corresponding decoding circuit receives a corresponding vertical word line signal, a corresponding global word line signal, and a corresponding sector supply voltage. The corresponding sector supply voltage is capable of supplying an erase voltage, such as xe2x88x929 V for a negative gate erase memory device, for example. With this arrangement, the corresponding decoding circuit is capable of selectively excluding the corresponding word line from receiving the erase voltage during the erase operation.
According to one particular embodiment, the corresponding word line is excluded from receiving the erase voltage based upon at least one of the corresponding vertical word line signal and the corresponding global word line signal. For example, the corresponding vertical word line signal can be switched between a negative voltage and zero volts, where if the vertical word line is switched to the negative voltage, the corresponding word line is excluded from receiving the erase voltage. As another example, the corresponding global word line signal can be switched between a positive voltage and a negative voltage, where if the corresponding global word line is switched to the negative voltage, the corresponding word line is excluded from receiving the erase voltage.
According to another embodiment, the memory circuit further comprises a plurality of local sector supply voltages. Each of the plurality of local sector supply voltages is supplied to the memory sector during the erase operation. In this particular embodiment, the corresponding sector supply voltage corresponds to one of the plurality of local sector supply voltages. The plurality of local sector supply voltages can be configured to supply either an erase voltage or a non-erase voltage independently of the others of the plurality of local sector supply voltages. With this arrangement, the corresponding word line is excluded from receiving the erase voltage by configuring at least one of the plurality of local sector supply voltages to supply the non-erase voltage.